1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to an isolation layer in the semiconductor device.
2. Description of the Related Art
Trench isolation methods are widely used in the manufacture of semiconductor integrated circuit devices because they ensure a narrow isolation distance and reduce the surface topology of a semiconductor substrate having an isolation layer. Particularly, the trench isolation methods prevent a punch-through phenomenon and reduce the thickness of an isolation layer, which are the problems of local oxidation of silicon (LOCOS) method, as the density of a semiconductor device increases. However, compared to the LOCOS method, the trench isolation methods are very complex.
In a typical trench isolation method, a trench is formed in a predetermined portion of a semiconductor substrate, and the trench is filled with a gap-filling insulating layer. Since the trench is formed by a dry etch method, e.g., a reactive ion etching (RIE) method, the inner wall of the trench can be damaged. Accordingly, a thermal oxide film is formed on the inner wall of the trench to prevent it from being damaged. In addition, to prevent the inner wall of the trench from being oxidized, a nitride liner, which is excellent for blocking the diffusion of oxygen, may be additionally formed on the thermal oxide layer, before filling the trench with a gap-filling isolation layer. However, when a nitride liner is formed, it tends to recess into the isolation layer when a pad nitride layer (used as an etching mask for forming an isolation trench) is removed, thereby causing a problem in subsequent process steps.
Referring to FIG. 1A, in a conventional trench isolation method, a mask pattern M including a pad oxide layer 102 and a pad nitride layer 104 is formed on a semiconductor substrate 100. Next, the semiconductor substrate 100 is etched to a predetermined depth using the mask pattern M as an etching mask, thereby forming a trench T. Thereafter, to repair damage to the inner wall of the trench T, a thermal oxide film 106 is formed on the inner wall of the trench T. Subsequently, to prevent oxidation of the inner wall of the trench T due to oxygen diffusion, a nitride liner 108 is formed on the thermal oxide film 106. Next, a gap-filling isolation (insulating) layer 110 is formed on the entire surface of the semiconductor substrate 100, and then the gap-filling isolation layer 110 is planarized to substantially the same level as the nitride liner 108 formed on the mask pattern M.
Referring to FIG. 1B, a wet etch process using phosphoric acid as an etchant is performed to remove the pad nitride layer 104 and the nitride liner 108 formed on the outside of the trench T. Unfortunately, the pad nitride layer 104 is overetched for it to be completely removed, the nitride liner 108 formed in the trench T is also etched. As a result, an undesirable divot 112 is produced in the trench T, and thus the nitride liner 108 is recessed from the top surface of the semiconductor substrate 100 by a distance D. Such recessed nitride liner 108 causes many problems in subsequent process steps as described below.
Referring to FIG. 1C, the resulting structure is planarized by a chemical mechanical polishing (CMP) method such that the level of the top surface of the gap-filling isolation layer 110 is substantially equal to the level of the top surface of the semiconductor substrate 100. As a result, an isolation layer 110xe2x80x2 is formed in the trench T. Next, the pad oxide layer 102 (of FIG. 1B) is removed using a HF solution. During the removal of the pad oxide layer 102, the side wall of the isolation layer 110xe2x80x2 exposed due to the divot 112 is also etched thereby expanding the lateral dimension of the divot 112. The divot 112 formed in the trench T causes a problem during subsequent steps of forming a gate electrode. In particular, to form the gate electrode, a thermal oxide film 114 is formed on the semiconductor substrate 100. Next, a polysilicon layer 116 is formed on the entire surface of the semiconductor substrate 100. The divot 112 formed in the trench T is filled with the polysilicon 116, thereby causing a bridge phenomenon between adjacent gate electrodes. Moreover, the operating characteristics of semiconductor devices, for example, threshold voltage, may be degraded due to the polysilicon filling the divot 112.
To solve the above problems, it is the first object of the present invention to provide a semiconductor device having an isolation layer with an improved structure.
It is the second object of the present invention to provide a method of manufacturing an isolation layer, in which fabrication is simplified and a divot is prevented from being formed in the isolation layer.
Accordingly, to achieve the first object, the present invention provides a semiconductor device having a Y-shaped isolation layer, which comprises side walls characterized by a first and a second slope on the sides of the isolation layer. A nitride liner and a thermal oxide film are preferably interposed between the first and second slopes and the semiconductor substrate.
The first slope is formed in the upper portion of the isolation layer and the second slope is formed in the lower portion of the isolation layer. The side wall with the first slope defines an interface between the upper surfaces of the nitride liner and the thermal oxide film, and the isolation layer, and the side wall with the second slope defines an interface between the side wall of the nitride liner and the isolation layer. The angle between the first slope and the second slope is preferably larger than 90xc2x0 and smaller than 180xc2x0.
To achieve the second object, the present invention provides a method of manufacturing an isolation layer, including the step of forming a trench in a semiconductor substrate. Next, a thermal oxide film is formed on the entire surface of the semiconductor substrate having the trench. Subsequently, a nitride liner is formed on the thermal oxide film. Thereafter, the nitride liner formed at the upper corners of the trench is removed while filling the trench with a gap-filling isolation layer. Next, the entire surface of the semiconductor substrate is planarized using the nitride liner as a planarization stop layer. Thereafter, the nitride liner acting as the planarization stop layer is removed.
The trench may be formed by performing the following process steps. First, a photoresist pattern, which is patterned to have the width of an isolation region, is formed on the semiconductor substrate. Next, the trench is formed in the semiconductor substrate by etching the semiconductor substrate to a predetermined depth using the photoresist pattern as an etching mask. Thereafter, the photoresist pattern is removed.
When removing the nitride liner formed at the upper corner of the trench and filling the trench with a gap-filling isolation layer, it is preferable that the nitride liner at the upper corners of the trench is separated or that the thickness of the nitride liner is reduced.
It is preferable to form the gap-filling isolation layer using a method for depositing a material layer and etching the deposited material layer concurrently in order to filling the trench with the gap-filling isolation layer while removing the nitride liner formed at the upper corner of the trench. For example, the gap-filling isolation layer may be formed by performing high-density plasma chemical vapor deposition (HDP CVD).
The gap-filling isolation layer may be formed by repeatedly and alternately processing the semiconductor substrate in a deposition apparatus and an etching apparatus in order to remove the nitride liner at the upper corners of the trench while forming the gap-filling isolation layer.
The gap-filling isolation layer may be formed using an apparatus which can perform a deposition process and an etching process in situ in order to remove the nitride liner at the upper corners of the trench while forming the gap-filling isolation layer.
The method of the present invention may also include the following steps after removing the nitride liner acting as a planarization stop layer. First, the thermal oxide film, which is exposed after the nitride liner is removed, is removed. Next, a sacrificial oxide film is formed on the semiconductor substrate exposed by removal of the thermal oxide film. Thereafter, ions are implanted in the entire surface of the semiconductor substrate having the sacrificial oxide film. Next, the sacrificial oxide film is removed.
When the gap-filling isolation layer is planarized using the nitride liner as a planarization stop layer, preferably, a chemical mechanical polishing method which uses slurries containing abrasives of the ceria family and/or surfactant having a strong anion property is used. The pH of the slurries is preferably approximately 7.
According to the present invention, formation of a divot at the boundary between an isolation region and an active region can be effectively prevented.